1. Technical Field
The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more particularly, to a phase change memory device having a dielectric layer for isolating contact structures formed by growth, a semiconductor device having the same, and methods for manufacturing the devices.
2. Related Art
Semiconductor memory devices include, among others, a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory. These semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. The volatile memory device is not capable of retaining the data stored therein when a power supplied to the memory is interrupted. In contrast, the nonvolatile memory device is capable of retaining data stored therein when a power supplied to the memory is interrupted, and therefore the nonvolatile memory device, and particularly the flash memory, is used for storing data. However, utilizing the flash memory for storing data has disadvantages in that it takes a long time to read and write data.
To overcome the above mentioned problems associated with the flash memory, several types of semiconductor memory including a ferro-electric RAM (FRAM), a magnetic RAM (MRAM), and a phase change RAM (PRAM) (hereinafter referred to as a “phase change memory device”) have been proposed in the art.
The phase change memory device includes a phase change material. For example, the phase or state of the phase change material can be changed between a crystalline state and an amorphous state upon the application of heat thereto, with the crystalline state having a resistance that is different than that of the amorphous state. The phase change material can be used as a storage medium in a memory device because the difference in resistance can be used to define the “states” of information (e.g., the different resistance may be used to define a logic ‘0’ state or a logic ‘1’ state). Accordingly, the phase change memory device is capable of performing a data reading operation by storing a data value therein.
A typical phase change memory device includes switching elements for selectively applying heat to the phase change material. The heat may be applied to the phase change material by applying a current to the phase change material. For example, the switching elements may be implemented using MOS transistors, bipolar transistors, diodes, or the like. PN diodes are often used as the switching elements in a phase change memory device in consideration of the area occupied by the switching elements.
When PN diodes are used as the switching elements, the PN diodes are vertically formed in an interlayer dielectric formed on a semiconductor substrate. The PN diodes may be formed through selective epitaxial growth (SEG) by employing the semiconductor substrate as a seed. Typically, a high density plasma (HDP) dielectric layer having excellent isolation and layer characteristics is used for isolating the PN diodes from each other.
Since the PN diodes have a vertical structure, the interlayer dielectric for isolating the PN diodes must be formed to a height corresponding to that of the PN diodes, for example, 2,000 Å or more.
In this regard, if the HDP dielectric layer, which constitutes the interlayer dielectric, is deposited as a thick layer having a thickness of 2,000 Å or over, the HDP dielectric layer applies compressive stress to the semiconductor substrate, which is composed of a silicon component. Due to the application of the compressive stress, the interlayer dielectric is likely to lift or peel from the semiconductor substrate, which results in a leakage current.
The interlayer dielectric is formed not only in a cell region, in which the PN diodes are formed, but also in a peripheral circuit region, in which driving transistors are formed. When HDP dielectric layer is formed over the driving transistors the driving characteristics of the MOS transistors are likely to deteriorate due to the compressive stress applied to the driving transistors by the HDP dielectric layer.
When defining contact holes for delimiting PN diode regions, stacking faults are likely to occur at the interfaces of the contact holes if the interlayer dielectric comprises a dielectric layer applying low compressive stress, for example, a tensile stress applying dielectric layer. In other words, when etching the tensile stress applying dielectric layer, a substantial amount of lattices are likely to be lost on the etching surfaces, that is, at the interfaces of the contact holes, resulting in the stacking faults. When SEG for forming the PN diodes is conducted with the stacking faults occurring in this way, portions where the stacking faults occurred serve as trap sites. As a consequence, the electrical reliability of the phase change memory device cannot be ensured because the PN diodes cannot be grown as a single crystal layer and have defects.